1. Field of the Invention
This invention relates to testing methods, and, more particularly, to a method of testing a semiconductor structure.
2. Description of Related Art
With the rapid development of electronic industry, electronic products are required to be compact-sized and low-profiled and having a variety of functionalities. The modern flip-chip technique can reduce the chip packaging area and shorten the signal transmission paths, and is thus applied to various chip packaging fields, such as chip scale package (CSP), direct chip attached (DCA) and multi-chip module (MCM).
In a flip-chip process, since the coefficients of thermal expansion (CTE) of a chip and a package substrate differs from each other significantly, bumps disposed on a periphery of the chip cannot be well bonded to corresponding contacts disposed on the package substrate, and are easily striped off from the package substrate. With the increasing integrity of an integrated circuit, the thermal stress and warpage generated due to the mismatch of the CTEs of the chip and the package substrate are server. As a result, the reliability of the chip between the package substrate is decreased, and the reliability test fails.
Besides, a plurality of chips are disposed on the package substrate in a two-dimensional manner. The package substrate has to have a great area, in order for more chips to be disposed thereon, which contradicts the compact-sized and low-profiled requirements of the modern electronic products.
In order to solve the above problem, a three-dimensional chip-stacking technique using a semiconductor substrate as an intermediate structure is brought to the market. A silicon interposer is disposed between a package substrate and a semiconductor chip additionally. Because the silicon interposer and the semiconductor chip are made of similar materials, the problem of mismatched CTEs is solved. A circuit is fabricated by a semiconductor wafer process on a side of the silicon interposer where the semiconductor chip is disposed, and contacts or a circuit of the semiconductor chip that are to be electrically connected to the circuit of the silicon interposer are also fabricated by the semiconductor wafer process. Therefore, a plurality of semiconductor chips can be disposed on the silicon interposer, even if the area of the silicon interposer is not enlarged. The semiconductor chips can be also stacked on one another, in order to meet the compact-sized and low-profiled requirements of the modern electronic products.
As shown in FIG. 1A, a plurality of conductive through-silicon vias (TSV) 100 are formed on a whole silicon substrate (not shown) or a whole wafer (not shown), upper and lower redistribution layers (RDL) 13a and 13b are formed on upper and lower sides of the silicon substrate, respectively, and a plurality of solder balls 14 are disposed on the lower redistribution layer 13B.
The silicon substrate is singulated to form a plurality of silicon interposers 10. A first semiconductor chip 11a (e.g., a functional chip) is disposed on each of the silicon interposers 10. A plurality of conductive bumps 110 are disposed on the upper redistribution layer 13a. A upper underfill 12a is formed between the first semiconductor chip 11a and the upper redistribution layer 13a to encapsulate the conductive bumps 110.
As shown in FIG. 1B, the silicon interposer 10 is disposed on the solder balls 14 and electrically connected to a package substrate 15. A lower underfill 12b is formed between the package substrate 15 and the lower redistribution layer 13b to encapsulate the solder balls 14.
As shown in FIG. 1C, a second semiconductor chip 11b (e.g., a functional chip) is disposed on the upper distribution layer 13a via a plurality of conductive bumps 110. The upper underfill 12a is also formed between the second semiconductor chip 11b and the redistribution layer 13a to encapsulate the conductive bumps 110. A semiconductor package 1 is thus fabricated.
The fabrication of the semiconductor package 1 is performed in cooperation with a test process. The test process first tests the electrical performance of the fabrication process shown in FIG. 1B, that is the electrical performance of the first semiconductor chip l la and the silicon interposer 10. A probe is connected to implant balls 150 disposed on the package substrate 15, to perform a first electrical test. After the first electrical test passes, the second semiconductor chip 11b is disposed on the silicon interposer 10, and a second electrical test is performed. Therefore, the overall electrical yield of the semiconductor package 1 is obtained.
However, the test method is performed after the silicon interposer 10 is disposed on the package substrate 15. Therefore, the test process will be performed slowly (because a conductive pathway has to pass an inner circuit of the package substrate 15. As a result, the operation time is long, and the throughout is low.
In the method of fabricating the semiconductor package 1, the formation of the conductive through-silicon vias 100 in the semiconductor chip and the silicon substrate is costly, and some of the interposers 10 may be defective (e.g., having silicon through vias that are defective and are not conductive). Therefore, after the semiconductor chips (e.g., the first and second semiconductor chips 11a and 11b) and the package substrate 15 undergo the electrical test, only the good semiconductor chip or the good package substrate 15 will be disposed on the interposer 10. However, the interposer 10 on which the good semiconductor chip or the good package substrate 15 are disposed may be defective, and the semiconductor chip or the package substrate 15, even though they are good to function, still have to be disposed as junk, together with the defective silicon interposer 10, after the first or second electrical test. For example, although the first semiconductor chip 11a passes the first electrical test, the second semiconductor chip 11b that is electrically connected to a conductive through-silicon via that is not conductive cannot pass the second electrical test, and the whole package has to be disposed as junk. Therefore, the fabrication cost of the overall semiconductor package 1 cannot be reduced.
Therefore, how to solve the problems of the prior art is becoming an urgent issue in the art.